I generally agree STRONGLY with all of your comments.

I would like to add that another issue is the need to have an understanding of what our quantitative performance results mean. As we test a system, we develop an understanding of what values to expect. Understanding one system can aid in understanding future systems. Some measurements are comparatively easy to understand, e.g., CPU utilization. Other measurements might be hard to understand or misleading, even for seasoned engineers.

For instance, I was talking to an experienced computer architect about cache miss rates. This person suggested an instruction-cache miss rate of 5% was not very high, which is a reasonable conclusion if you are familiar with DATA cash miss rates, but it is not correct for contemporary instruction caches.

A common instruction cache line size today is 32 bytes. This means that if each instruction requires 4 bytes, 8 instructions fit in a cache line. Thus, if we are executing straight-line code (no branches), the highest miss rate we will see is if we miss each time we enter a new cache line, which happens 1/8th of the time. This miss rate is 12.5%

Of course, because of branches, we enter new cache lines more often than once every 8 instructions. But, because of loops, we end up with long periods of execution during which we will see no or very few instruction cache misses.

A high instruction cache miss rate for the processor above is about 2-4%. I follow the rule that this can be reasonably compared to a DATA cache miss rate by multiplying by the number of instructions which fit in a line. In this case, the result is 16-32% for a data cache, which falls into the range of what we would commonly call a high miss rate for an L1 data cache.

Cheers!

-Todd

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Todd Bezenek
Computer Architect and Performance Engineer